1. Field of the Invention
The present invention relates to a multilayer capacitor array, and more particularly, to a multilayer capacitor array capable of embodying high capacitance, preventing crosstalk between capacitor devices and delamination between layers, and having low equivalent series inductance (ESL) characteristics.
2. Description of the Related Art
Multilayer capacitor arrays are very useful to reduce a mounting area for a plurality of multilayer capacitor devices. To increase a mounting density, there are provided various multilayer capacitor arrays integrating a plurality of multilayer capacitor devices into one chip. To reduce a mounting area, multilayer capacitor devices are provided in a capacitor array, one chip, as possible. FIG. 1A is a perspective view illustrating a conventional multilayer capacitor array 1, and FIG. 1B is a top view illustrating a conventional structure of internal electrodes.
Referring to FIG. 1, the multilayer capacitor array 1 includes a capacitor body 2 and external electrodes 5, 6, 7, and 8 formed on sides of the capacitor body 2. In the capacitor body 2, a dielectric layer 3 on which electrode plates 5a and 7a, separated from each other, are printed and a dielectric layer 4 on which electrode plates 6a and 8a, separated from each other, are printed are alternately deposited. The respective electrode plates 5a to 8a include leads or drawn portions 5b to 8b connected to correspondent external electrode 5 to 8.
In the capacitor array 1, two multilayer capacitor devices independent from each other are formed. One of the capacitor devices, a first multilayer capacitor device, is formed by alternately arranging the electrode plates 5a and 6a of different polarities. Another of the capacitor devices, a second multilayer capacitor device, is formed by alternately arranging the electrode plates 7a and 8a of different polarities. A plurality of the electrode plates 5a and 6a form the first capacitor device, and a plurality of the electrode plates 7a and 8a form the second capacitor device.
FIG. 2A is a circuit diagram illustrating an example of the multilayer capacitor array of FIG. 1A, and FIG. 2B is an equivalent circuit diagram illustrating the example of FIG. 2A. For example, the capacitor array 1 may be used as an electromagnetic interference (EMI) filter removing noise of signal lines S1 and S2 different from each other or a decoupling capacitor connected to source lines P1 and P2 different from each other.
For example, the external electrodes 5 and 7 may be connected the signal lines S1 and S2 as (+) terminals, respectively, and the external electrodes 6 and 8 may be connected to a ground as (−) terminals. The respective capacitor devices in the capacitor array 1 have not only capacitance but also parasitic inductance and resistance. Accordingly, as shown in FIG. 2B, the respective capacitor devices in the capacitor array 1 may be shown as capacitances C1 and C2, inductances L1 and L2, and resistances R1 and R2 connected in series. The inductances L1 and L2 and resistances R1 and R2 may be regarded as equivalent serial inductances (ESLS) and equivalent serial resistances (ESRs) of the respective capacitor devices.
As described above, connecting respective capacitor devices in a capacitor array to different signal lines S1 and S2, two EMI filter may be embodied by one chip. Also, the capacitor array 1 may be used as decoupling capacitors of a power circuit, connected to different lines P1 and P2 and corresponding to the respective lines P1 and P2.
When using the capacitor array 1, a mounting area may be more reduced than a case of using a plurality of capacitor chips. However, using an internal electrode divided in the same plane, for example, (+) electrode divided into 5a and 7a, flaking between layers, that is, delamination may occur. Also, when dividing the internal electrode in the same plane, due to a gap that is a dielectric material portion between electrode plates in the same plane, substantial decrease of an electrode area is caused, thereby generating a considerable capacitance loss.
In addition, in a situation where a demand for a capacitor with a low ESL in a high frequency circuit is currently increased, it is difficult to obtain an ESL low enough by the capacitor array 1. Furthermore, as shown in FIG. 2C, an electromagnetic interference phenomenon due to stray capacitance may easily occur between the two electrode plates 5a and 7a disposed in a line in the same plane, thereby generating crosstalk between two capacitor devices disposed in series.